FIG. 2a shows the signals on a conventional source synchronous serial link, where the data signal is accompanied by a clock signal sent from transmitter to receiver such that a rising edge on the clock signal occurs at the same time as each transition on the data signal. The receiver then samples data on the falling edge of clock.
As will be familiar to a person skilled in the art, data may alternatively be transmitted using a data line and an associated strobe line. A data signal carrying the actual data to be communicated is transmitted on the data line, and an associated strobe signal is transmitted on the strobe line to aid in validating the sampling of that data at the receiver.
The strobe signal shown in FIG. 2b is an alternative to the clock signal of FIG. 2a. The strobe signal is used to transmit information allowing the transmitter's clock signal to be recovered at the receiver.
The data signal carries the raw data, and the strobe signal changes state whenever the data signal does not. That is, as illustrated in FIG. 2b, when two consecutive data bits of the same value are transmitted in the data signal, a logical transition is signalled in the strobe signal to delineate between those two bits. So for the first of two data bits of the same value the strobe is at a first logical level, and at the beginning of the second of those two bits the strobe signal transitions to the opposite logical level. The strobe signal then remains at that opposite logical level until the next time a data bit is transmitted having the same value as the previous bit (which could happen at the next bit if three bits of the same value are transmitted, or at a subsequent pair of bits).
In the example of FIG. 2b, a sequence of bits 0100111 is shown as being transmitted in the data signal. Throughout the first three data bits 010, the data changes at every bit and so the strobe remains at a constant logical level (in this case logic-zero). However, the fourth data bit is a 0, the same as the third. Therefore the strobe signal changes to the opposite logical level (in this case logic-one) for the duration of the fourth data bit. The fifth data bit is a 1, different to the fourth, so the strobe signal remains a constant logical level from the fourth to the fifth bit. But the sixth and seventh data bits are then both also 1, the same as the fifth, so the strobe changes back to the first logical level (logic zero) for the duration of the sixth data bit and then back again to the opposite logical level (logic one) for the duration of the seventh data bit.
Because one of the data or the strobe signal, but not both, always changes logical level at the boundary between every data bit, then the XOR of the data and strobe signal will recover the transmitted clock signal as shown. Thus a clock signal can be recovered at the receiver by taking the XOR of the data and strobe signals. This technique is sometimes known is “non-return to zero data-strobe encoding”.
The difference over the clock signal of FIG. 2a is that either a rising or falling clock edge of the recovered clock may occur for each data bit. This has the advantages of greater tolerance of timing skew between the data and strobe signals than between the data and clock signals and lower average energy per bit (since the strobe signal need only change state when data signal does not).
Examples of this data/strobe technique are found in the physical layer interface for packet data connections in many applications, particularly in serial links, for example between a baseband modem device and an application processor device in the MIPI HSI standard. That is, the Mobile Industry Processor Interface (MIPI) Alliance standard for High-Speed Synchronous Serial Interface (HSI) physical layer version 1.0, available from the MIPI website www.mipi.org. Other applications are standardised in IEEE 1394 (FireWire) and IEEE 1355.
However, the situation described in relation in FIG. 2b is somewhat idealised. As the data rate is increased, the impact of timing uncertainties in the link on the bit time available for sampling at the receiver becomes more severe. Timing uncertainties include clock jitter in the transmitter and other factors, but the dominant contribution to timing uncertainty is the timing skew introduced between the data and strobe signals due to mismatch in the electrical delays on the data and strobe paths between the transmitter device and the receiver device. This includes mismatches within the transmitter and receiver devices themselves and also in the connection between the two, e.g. a wired connection such as on a circuit board on which the transmitter and receiver are both mounted.
A more realistic situation is shown in FIG. 2c, where a timing skew has developed between the received data signal and the received strobe signal. In this example, the data signal lags the strobe signal by a time Tskew. FIG. 2d shows an enlarged portion A from the timing diagram of FIG. 2c. 
Typically the data/strobe receiver is part of a larger integrated circuit, so the data packet or frame which is extracted by the receiver needs to be transferred to a system clock which is asynchronous to the timing of the serial link. For mobile applications especially the transmitter data rate may vary between the maximum rate and zero as a function of the functional or power saving mode of the transmitter and the system clock frequency in the receiver may vary as a function of the power saving mode of the receiver. Therefore it is desirable for the receiver to operate over a range of data rates and system clock frequencies without requiring an exact relationship between the two. Furthermore it is desirable to be able to receive variable-length frames as required in the MIPI HSI standard referenced above. Most importantly, it is desirable to minimise the effect of timing skew, which reduces the bit time at the receiver thereby limiting the rate at which data can be transmitted and still successfully sampled at the receiver.
One type of receiver design which is known in the prior art is called here an “over-sampling receiver” and shown in FIG. 1. This receiver comprises a pair of flip-flops 7 disposed at each of the data and strobe inputs, each pair arranged as a short two-bit long shift register with inputs connected to receive the data and strobe signals respectively. The clock input of each flip flop 7 of each shift register is connected to the system clock (SYSTEM_CLK), and the output of each shift register is connected to the receiving logic 9 in the system clock domain. The function of the shift registers 7 is to resolve meta-stability in crossing between clock domains.
The over-sampling receiver operates by directly sampling the data and strobe signals using the system clock, i.e. by clocking the data and strobe signals through the flip-flops 7 of the respective shift registers into the receiving logic 9 in dependence on the system clock signal SYSTEM_CLK. The de-serialisation and de-framing of the data is implemented entirely in the system clock domain. While this is the simplest design, it has the disadvantage that the system clock must run fast enough to directly sample the data/strobe signals in the presence of timing uncertainty. It can be seen from FIG. 2d that the maximum sampling period for each of the data and strobe signals in this case is Tbit−Tskew and therefore the timing skew directly increases the minimum sampling system clock frequency. For example if the maximum timing skew is half the nominal bit time as is specified in the MIPI HSI standard, the system clock frequency must be more than twice the data rate. The requirement for increased minimum system clock frequency will typically affect the power consumption for entire receiving device not just the receiver circuit itself. So for a data rate of 100 Mbps as is typical in the MIPI HSI standard, a system clock speed of greater than 200 MHz is required even when the receiver is in a low-power mode.
Another type of receiver known in the prior art is called here an “asynchronous receiver” shown in FIG. 3. This receiver comprises a series of first D-type flip-flops 7 and a series of second D-type flip-flops 7′ disposed at the data input, each series arranged as a shift register with its input connected to receive the data signal. The receiver also comprises an XOR gate 8 with one input connected to the data input, the other input connected to the strobe input, and its output connected to the clock inputs of each of the flip-flops 7 and 7′ of the shift registers. The first flip-flops 7 are a positive (rising) edge triggered flip-flops and the second flip-flops 7′ are negative (falling) edge triggered flip-flops. The receiver further comprises buffer register 11 and related logic connected to receive the output of all but the last flip-flop 7 and 7′ in each shift register series, and to provide an output to the receiving system clock domain logic 9. The receiver further comprises valid logic 10 connected to the final flip-flops 7 and 7′ of each register and the buffer register and related logic 11, and two additional first flip-flops 7″ clocked by the system clock signal SYSTEM_CLK connected between and the receiving logic 9 and valid logic 10 with related logic.
In operation, the XOR gate 8 recovers the transmit clock as the XOR of the data and strobe signals, and provides the recovered clock signal to the clock inputs of each of the flip-flops 7 and 7′ of each shift register. The recovered clock is thus used to clock a “double edge triggered” (DET) circuit, i.e. whereby the two shift registers consisting of the flip-flops 7 and 7′ are triggered on the positive and negative edges of the recovered clock respectively. Data is shifted from left to right as each transition occurs on the recovered clock. A flag bit is initially set in the leftmost flip-flop of each chain. When this flag reaches the rightmost bit of either chain, it indicates to the valid logic 10 that a complete data frame has been received and causes the contents of the two shift registers to be copied to a buffer register 11 after which the data is synchronised to the system clock domain 9 using the additional flip-flops 7″. Alternatively a bit counter may be employed to detect the end of frame. Note, the output of the XOR gate 8 is slightly delayed relative to the data input, so that the first flip-flop in each shift register does not attempt to sample on a data edge.
Looking at FIGS. 2c and 2d, it can be seen that the DET circuit thus has a “received bit time” of either Tbit+Tskew, Tbit, or Tbit−Tskew depending on the data at the time. The performance of the receiver is limited by the lowest bit time it can handle.
While this asynchronous receiver does not have the over-sampling requirement of the design in FIG. 1, it has the disadvantage that most of the receiver circuit must operate at the DET rate which is set by the lower of the received bit times Tbit−Tskew. The relative complexity of the DET circuit results in large logic path delays between flip-flops which limits the bit time that the receiver can handle, resulting in lower data rate and poorer skew tolerance.
Further, this asynchronous receiver requires a shift register long enough to hold an entire frame, a buffer register 11 of the same size and handshake logic to control the loading of the buffer register 11 and the transfer to the system clock domain 9. This logic is complicated by the fact that when the frame length N is odd there will be for example (N−1)/2 bits in the positive edge triggered flip-flops and [(N−1)/2]+1 bits in the negative edge triggered flip-flops 7′ at the end of one frame and the reverse on the next frame.
Variations of the asynchronous receiver are also known in the prior art which reduce the length of the positive and negative edge triggered shift registers and the holding register. This can be done by transferring M data bits at a time to the holding register where M<N (where N is the frame length). However this approach has significant disadvantage that it is not possible for the receiver to handle arbitrary frame size because M must divide N—otherwise the final (N modulo M) bits of the frame may remain undetected in the shift register indefinitely at the end of a received frame until the next frame arrives. This can affect system performance if the frame is for example a timing-critical control packet or a data packet requiring low latency transfer.
Other variations of the asynchronous receiver design in the prior art dispense with the need to detect the completion of a frame (or part of a frame) in the shift registers by relying on a fixed frequency relationship between the recovered clock and the (asynchronous) system clock. However these approaches do not allow the link to operate over the full range of possible data rates and system clock frequencies depending on the functional or power saving states of the transmitter and receiver.